shifuy resten - EX STAGE IF STAGE ID STAGE BRANCH ADDRESS PATH MEM STAGE WB STAGE instruction is shifted to u IF/ID ID/EX ALU FORWARDING PATH EX/MEM MEM/WB MUX REGISTER FILE FROM PC FROM REG - MUX w two- READ PORT FROM REG - WRITE PORT IMMEDIATE Figure 2-6a.. Block diagram for a pipelined microprocessor 1-wcwo-wc-ZUHU WRITE REGISTER SELECT READ PORT ZO--C-02- -ZDU-OZ READ -OZ INSTRUCTION MEMORY DATA MEMORY MEMORY FORWARDING PATH CONTROLLER 6. The pipelined microprocessor in Figure 2-6a has five stages, so 5 instructions are executing at any given time and one instruction completes every clock cycle. The ideal speedup of this machine over that of a non-pipelined machine that only completes an instruction every 5 clock cycles is then 5. It would seem that decreasing the amount of work per stage and increasing the number of stages would allow the pipeline to be clocked faster and give an even greater speedup. Use an automobile assembly line analogy for a pipelined processor to help you think of some possible problems with, for example, building a pipeline with 40 stages. shifuy resten - EX STAGE IF STAGE ID STAGE BRANCH ADDRESS PATH MEM STAGE WB STAGE instruction is shifted to u IF/ID ID/EX ALU FORWARDING PATH EX/MEM MEM/WB MUX REGISTER FILE FROM PC FROM REG - MUX w two- READ PORT FROM REG - WRITE PORT IMMEDIATE Figure 2-6a.. Block diagram for a pipelined microprocessor 1-wcwo-wc-ZUHU WRITE REGISTER SELECT READ PORT ZO--C-02- -ZDU-OZ READ -OZ INSTRUCTION MEMORY DATA MEMORY MEMORY FORWARDING PATH CONTROLLER 6. The pipelined microprocessor in Figure 2-6a has five stages, so 5 instructions are executing at any given time and one instruction completes every clock cycle. The ideal speedup of this machine over that of a non-pipelined machine that only completes an instruction every 5 clock cycles is then 5. It would seem that decreasing the amount of work per stage and increasing the number of stages would allow the pipeline to be clocked faster and give an even greater speedup. Use an automobile assembly line analogy for a pipelined processor to help you think of some possible problems with, for example, building a pipeline with 40 stages