Show the forwarding and stalls needed to execute the following instructions on the pipelined MIPS processor. Draw an arrow showing forwarding between the stage that provides the data and the stage that receives the data. Show all stall cycles by placing an $x$ in the box to represent a stall cycle.

$Iw$ $$t1,4($$$t2)$

addi $$t0,$$$t1,100$

$Iw,$$$t2,4($$$t0)$

add $$t3,$$$t1,$$$t2$

$sw$ $$t3,-32($$$t0)$

sub $$t3,$$$t3,10$