Show the organization (block level design) of a word-addressable RAM with capacity of 8,192 bits and word size of 8 bits, using coincident encoding. Show all the components, including decoders, address lines, and the internal memory organization, similar to the figure. Clearly specify the size of the memory, including the number of rows and columns (each columns corresponding to a word) and the number of AND gates in each decoder.

Address inputs Memory EN enable Read Write Word 0 Word decoder Word 2 Word 3 Input data Output data BC