Show the pipeline timing diagram for one iteration of the loop using the classic five-stage MIPS Architecture. For all parts, assume that register read and register write can be done in the same clock cycle and branches are resolved in EX stage (i.e., the branch target address will be known at the end of EX stage and the target instruction can be fetched in the next clock cycle). There is no branch prediction mechanism employed. loop: 1w s1, 0 (s2) addi s1, s1, 1 SW s1, 0 (s2) addi s2, s2, 4 sub s4, s3, s2 bne s4, zero, loop a. Show the pipeline timing diagram of this instruction sequence assuming forwarding is not supported by the architecture. b. Do the same work in part (a) assuming forwarding is fully supported by the architecture