Show the timing of this instruction sequence for the DLX pipeline with normal forwarding hardware. Assume that the branch is handled by predicting it with a $1$ bit branch prediction which initially assume the branch is not taken. $($write what pipeline stage the instruction is passing through at each clock cycle $[$IF$,$ ID$,$ EX$,$ ME$,$ WB$],$ or stall if it is stalling or flush if it is being flushed, leave it blank if the instruction is complete or has yet to begin being processed$).$

$\backslash$table$[[$Instructions:$,],[1,$lw $$t1,4($$$sp)$# loads $1$ into $t$1],[2,$lw $$t0,0($$$sp)$# loads $0$ into $$t0$

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