Shown below are the contents of all the relevant (and some irrelevant) registers after the completion of three SUCCESSIVE clock cycles which are part of the instruction cycle for NOTE: The start of the FETCH phase is before clock cycle N and memory is not accessed during clock cycles N, N+1, N+2. Clock IR MAR MDRROR1 R3 R4 R5 R6 R7 Cycle a x4010 a xC89A xA1B1 x1234 x2222 x2345 x8333 x 5678x0OFF xC89A xA1B1 x1234 x2222 x2345 x8333 x 5678 x0OFF N+2 | | x833A | xA 1B1 | xC89A | xA 1B1 | x1234 | x2222 | x2345 | x8333 | x 5678 | x00FF (a) Which states in the LC3 state machine correspond to the processing in t e cycles N, N+1, N+2? Give only the state numbers. (HINT: refer to the state machine graph in Appendix C (b) What is the address of the instruction being processed? Give your answer in hexadecimal c) Write down i he bilary coding of i he msirlielon leng proc(nd. I l NT: yon al: i refer in your text book page 568) notation to the LC-3 state machine for this question) Shown below are the contents of all the relevant (and some irrelevant) registers after the completion of three SUCCESSIVE clock cycles which are part of the instruction cycle for NOTE: The start of the FETCH phase is before clock cycle N and memory is not accessed during clock cycles N, N+1, N+2. Clock IR MAR MDRROR1 R3 R4 R5 R6 R7 Cycle a x4010 a xC89A xA1B1 x1234 x2222 x2345 x8333 x 5678x0OFF xC89A xA1B1 x1234 x2222 x2345 x8333 x 5678 x0OFF N+2 | | x833A | xA 1B1 | xC89A | xA 1B1 | x1234 | x2222 | x2345 | x8333 | x 5678 | x00FF (a) Which states in the LC3 state machine correspond to the processing in t e cycles N, N+1, N+2? Give only the state numbers. (HINT: refer to the state machine graph in Appendix C (b) What is the address of the instruction being processed? Give your answer in hexadecimal c) Write down i he bilary coding of i he msirlielon leng proc(nd. I l NT: yon al: i refer in your text book page 568) notation to the LC-3 state machine for this question)