Simple Verilog Design and Simulation

Xilinx ISE

1. Create a project named CSC340Lab2 in ISE.
2. Write a Verilog module called myAnd to implement the logic AND gate.
3. Write a test bench to test the myAnd module created in step 3. Simulate the circuit using ISim and analyze the resulting waveform.
4. Take full screenshots of the source code of myAnd module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.
5. Write a Verilog module called myOr to implement the logic OR gate.
6. Write a test bench to test the myOr module created in step 6. Simulate the circuit using ISim and analyze the resulting waveform.
7. Take full screenshots of the source code of myOr module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.
8. Take full screenshots of the source code of myOr module and the test bench Verilog file to be included in the lab report.
9. Write a Verilog module called myNot to implement the logic NOT gate.
10. Write a test bench to test the myNot module created in step 10. Simulate the circuit using ISim and analyze the resulting waveform.
11. Take full screenshots of the source code of myNot module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.