Single digit stop-watch in Verilog Your design will be a single (decimal) digit stop-watch with start/resume, stop, reset buttons. The functions for each of the input buttons are as follows: Start/Resume This button is used to trigger the counting on the stop-watch. When this input is activated from an initial state, the watch advances every second counting from 0 to 9 and then looping back to 0. The counting process should just keep on running until and unless any other input (stop or reset) is activated If this input is activated from a previous steady display on the watch, then the watch resumes counting every second from that particular display value. Stop This button is used to stop the stopwatch counting and to hold the display. When this button is pressed the stopwatch stops counting at the very instance and displays the time (in seconds) continuously, until any other input (resume/reset) is pressed Reset - This button is used to reset the stopwatch display to 0. When this button is pressed, irrespective of the state of your counter, your stop watch is reset to zero (the display should read 0) and should hold this value zero until the start/resume button is activated. A. Input-Output Interface Use any of the (push) buttons available on the FPGA board as the inputs and the 7-segment display LED on the board to display the output. You are to program the FPGA on the Nexys board with the necessary code to achieve the above stopwatch design. How to Track Time? Use the internal clock on the Nexys board as the reference for computing time. Hint: If I have a clock running at 60 MHZ how many positive edge triggers will I observe in 1 second? The intellectual challenge here is to do the necessary "clock division" within your Verilog code to increment the counter every second. You will have to refer to the clocking issues on the Nexys board, see page 11/12 of the Nexys Reference Manual, Doc 502-182, uploaded on the class website with all the information/documentation regarding your lab kit, near Lab 1. The TAs will also educate you about the clocking issues in the lab. . Write a behavioural Verilog description for the stopwatch . Write a testbench to simulate your design "exhaustively" Single digit stop-watch in Verilog Your design will be a single (decimal) digit stop-watch with start/resume, stop, reset buttons. The functions for each of the input buttons are as follows: Start/Resume This button is used to trigger the counting on the stop-watch. When this input is activated from an initial state, the watch advances every second counting from 0 to 9 and then looping back to 0. The counting process should just keep on running until and unless any other input (stop or reset) is activated If this input is activated from a previous steady display on the watch, then the watch resumes counting every second from that particular display value. Stop This button is used to stop the stopwatch counting and to hold the display. When this button is pressed the stopwatch stops counting at the very instance and displays the time (in seconds) continuously, until any other input (resume/reset) is pressed Reset - This button is used to reset the stopwatch display to 0. When this button is pressed, irrespective of the state of your counter, your stop watch is reset to zero (the display should read 0) and should hold this value zero until the start/resume button is activated. A. Input-Output Interface Use any of the (push) buttons available on the FPGA board as the inputs and the 7-segment display LED on the board to display the output. You are to program the FPGA on the Nexys board with the necessary code to achieve the above stopwatch design. How to Track Time? Use the internal clock on the Nexys board as the reference for computing time. Hint: If I have a clock running at 60 MHZ how many positive edge triggers will I observe in 1 second? The intellectual challenge here is to do the necessary "clock division" within your Verilog code to increment the counter every second. You will have to refer to the clocking issues on the Nexys board, see page 11/12 of the Nexys Reference Manual, Doc 502-182, uploaded on the class website with all the information/documentation regarding your lab kit, near Lab 1. The TAs will also educate you about the clocking issues in the lab. . Write a behavioural Verilog description for the stopwatch . Write a testbench to simulate your design "exhaustively
