single-cycle design

MIPS assembly languange

Suppose that in n a particular implementation of the MIPS single-cycle design, the lw instruction takes the longest amount of physical time to execute at 3.5 ns. What would be the theoretical maximum clock rate this circuit could run at (note that the actual clock rate would likely be a little bit less than this because we have to account for propagation delays through data path gates and for signal rise and fall times).

Instruction 125-0) Jump address [31-0] Shift eft 2 28 PC 4 [31-28] 26 PC Src M Add Mux 1 x PC Src Branch Add Add result Mux 2 PC Mux 1 Shift RegDst PC Adder Select left 2 Branch AND Branch Gate Mem Read Instruction 31-26] MemtoR Control ALUO MemWrite ALUSrc RegWrite ALU Src2 Instruction 125-21] Read Mux Read register 1 Read PC address Instruction [20-16] Read data 1 register 2 Write Read ALU ALU Result register data 2 IM result Address M Mux data Instruction [31-0] M Instruction Instruction 115 111 X memory Write data Registers Data Write Dst Reg memory 16 Instruction [15-01 Sign ALU extend control ALUOplnput Instruction (5-0] Instruction 125-0) Jump address [31-0] Shift eft 2 28 PC 4 [31-28] 26 PC Src M Add Mux 1 x PC Src Branch Add Add result Mux 2 PC Mux 1 Shift RegDst PC Adder Select left 2 Branch AND Branch Gate Mem Read Instruction 31-26] MemtoR Control ALUO MemWrite ALUSrc RegWrite ALU Src2 Instruction 125-21] Read Mux Read register 1 Read PC address Instruction [20-16] Read data 1 register 2 Write Read ALU ALU Result register data 2 IM result Address M Mux data Instruction [31-0] M Instruction Instruction 115 111 X memory Write data Registers Data Write Dst Reg memory 16 Instruction [15-01 Sign ALU extend control ALUOplnput Instruction (5-0]