Sketch the state transition diagram for the FSM described by the following SystemVerilog code.

module fsm2( input logic clk, reset, input logic a, b, output logic y); logic [1:0] state, nextstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; always_ff @(posedge clk, posedge reset) if (reset) state

Sketch the state transition diagram for the FSM described by the following SystemVerilog code. module fsm2( input logic clk, reset, input logic a, b, output logic y); logic [1:0] state, nextstate; parameter S0 = 2 'b00; parameter S1 = 2 'b01; parameter S2 = 2'b10; parameter S3 = 2 'b11; always.ff @(posedge clk, posedge reset) if (reset) state