SO a = In 1 b = In2 Q5. The FSMD of the circuit is given below implementing following equation: Y = (t1 t2) + min (0.5t1, 0.875t2), where t1 = |a| and t2 = 16|| Show the variable usage table and apply the optimization of variable merging for minimizing the number of required registers by using compatibility graph. Assume the following functional units are available: abs, shift, adder, subtractor, adder/subtractor and min. Show the Optimized datapath using 2 abs, 2 shifters, adder/subtractor Start $1 t1 = |al t2 = lbl and a min unit. (15) S2 t3 = t1-t2 t4 = t1 >> 1 t5 = t2 >> 3 53 t6 = t2 t5 54 t7 = min (t4, 16) 60 la t8 = t3 +t7 S6 Y=t8 Done = 1 SO a = In 1 b = In2 Q5. The FSMD of the circuit is given below implementing following equation: Y = (t1 t2) + min (0.5t1, 0.875t2), where t1 = |a| and t2 = 16|| Show the variable usage table and apply the optimization of variable merging for minimizing the number of required registers by using compatibility graph. Assume the following functional units are available: abs, shift, adder, subtractor, adder/subtractor and min. Show the Optimized datapath using 2 abs, 2 shifters, adder/subtractor Start $1 t1 = |al t2 = lbl and a min unit. (15) S2 t3 = t1-t2 t4 = t1 >> 1 t5 = t2 >> 3 53 t6 = t2 t5 54 t7 = min (t4, 16) 60 la t8 = t3 +t7 S6 Y=t8 Done = 1