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5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Index 9-5 Offset Tag 31-10 5.3.1 [5] What is the cache block size (in words)? -Since block size can be determined by the offset bits. In this question we have 4 offset bits (0-4), therefore we have 25 or 32 words in a block (basic binary problem). 5.3.2 [5] How many entries does the cache have? 5.3.3 [51 What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 considering a simple scenario with no dirty bit of valid bit for each line of the cache, we need 54 bits for tag field, and 32 words of suppose size w each. Therefore Total bits/Total data bits (54+32w)/(32"w). 5.3.4 [10] How many blocks are replaced? 5.3.6[10] What is the hit ratio? 5.3.6 [20]