Source and drain junctions with step junctions were fabricated using p-type Si wafer uniformly doped with Na = 10^16/cm3. At this time, the dopant concentration (Nd) constituting the source and drain junction is 1 x 10^19/cm3. T=300K. Answer each question below.

(1) Calculate the energy barrier value formed between the drain and Si substrates in a thermal equilibrium state without applying the gate voltage (G) and drain voltage (d). At this time, the intrinsic carrier concentration ni=1.5x10^10/cm3.

(2) Calculate the width (W) of the depletion layer under thermal equilibrium and analyze the results.

(3) When d = +5 under floating gate voltage (i) How does the energy barrier change? And (ii) how does the deprivation layer change?