sro sro d d 1 1 SENDER sr1 sr1 ADAPTOR rr rr RECEIVER 1 1 sa sa ra ra The purpose of this controller is to adapt the interfaces of SENDER and RECEIVER so that they can communicate. SENDER communicates one bit of data per cycle by initiating a handshake, either sr/sa to communicate logic-0 or sr1/sa to communicate logic-1. SENDER guarantees that these handshakes do not overlap in time, in particular sro and sr1 are mutually exclusive. RECEIVER accepts one bit of data per cycle by participating in the handshake rr/ra and reading value d as follows. Once it receives a read request rr+, it assumes that d is stable and remains stable until a read acknowledgement ra+ is issued, and its value represents the bit of data being communicated. So RECEIVER reads d after rrt, and then completes the rest of rr/ra handshake. Since SENDER and RECEIVER use incompatible protocols, they need an adaptor to communicate, as shown in the above picture by the ADAPTOR block. On each cycle of communication, ADAPTOR participates in a handshake initiated by SENDER, either sr/sa or sr/sa, sets the value of d accordingly, and initiates the handshake rr/ra with RECEIVER. For efficiency, ADAPTOR should maximise the concurrency between its actions, while still maintaining the correct operation. Thus, it should produce its outputs as soon as this is allowed by the handshake protocol and the logic of operation as explained above. E.g., ADAPTOR may complete the handshake with SENDER (and accept srO+ or sr1+ for the next cycle) before its handshake with RECEIVER completes. Specify the behaviour of ADAPTOR as a Signal Transition Graph. You can assume that the environment (the dashed boxes in the picture) fulfils its contract, as described above. If necessary, you may make additional assumptions to clarify any potential ambiguities in the above description - such assumptions (if any) must be explicitly stated and justified. You are not required to design a circuit