sub $t0, $t2, $t3 addi $s0, $t0, -7 add $s1, $s0, $t5 Iw $t6, 6($s1) sub $s0, $16, $12 Consider the above code sequence, a) If you only use stall to overcome the data hazards in the above code sequence, how many stalls would be needed? Answer: b) If you use stall and code scheduling to overcome the data hazards, what will be the number of clock cycles? Answer: c) If you use stall and forwarding to overcome the data hazards, how many stalls would be reduced? Answer: d) What will be the CPI, if you use stall and forwarding to overcome the data hazards? Answer: e) Consider the clock period is 500ps. Consider, the Register Write takes 450ps and Register Read takes 350ps, how many stalls would be needed to overcome the data hazard if you use only stall as a solution? Answer: f) If the "lw $16, 6($s1)" instruction in the above code sequence is replaced with "sw $t6, 6($s1)", what will be the number of clock cycles If you use forwarding to overcome the data hazards? Answer: g) If the instruction "add $s7, $t2, $t3" is added at the end of the above code sequence, what will be the total number of clock cycles if only stall and forwarding is used to overcome the data hazards? Answer:

#kindly give all ans.