sub $to, $80, $s1 add $80, $t0,$t1 lw $t0, 0 ($80) sw $t0, 8 ($80) add Sto, Sto. $t1 sw $t0, 0 (0) (15 points) Assuming a 5.stages pipelined processor has no forwarding, populate the following pipeline diagram using the compact notation Ute 5 for stalls TI 12 12 ta 1 a. [15 points] Assuming a stages pipelined processor has no forwarding populate the following pipeline diagram using the compact natation Use for stails. 10 TI TH + TIL TIL TH b 125.points) Assumint Sistare pipelined processor has full forwarding populate the following pleine diagram using the compart notation uses for sale TE amb Ste, $20, 331 add $20, $to, 301 lv Sto, 050) add Sto, 30, 31 2 Sto, o (520) b. [15 points) Assum TO 3toa, ! - Sad, 3, 9.3 a. ES sub $to, $80, $s1 add $80, $t0,$t1 lw $t0, 0 ($80) sw $t0, 8 ($80) add Sto, Sto. $t1 sw $t0, 0 (0) (15 points) Assuming a 5.stages pipelined processor has no forwarding, populate the following pipeline diagram using the compact notation Ute 5 for stalls TI 12 12 ta 1 a. [15 points] Assuming a stages pipelined processor has no forwarding populate the following pipeline diagram using the compact natation Use for stails. 10 TI TH + TIL TIL TH b 125.points) Assumint Sistare pipelined processor has full forwarding populate the following pleine diagram using the compart notation uses for sale TE amb Ste, $20, 331 add $20, $to, 301 lv Sto, 050) add Sto, 30, 31 2 Sto, o (520) b. [15 points) Assum TO 3toa, ! - Sad, 3, 9.3 a. ES