Suppose a 64-bit wide memory bus has a latency of 100 CPU cycles before transferring the data. Suppose the memory bus has a bandwidth of 2 gigabytes per second. Assuming the CPU clock frequency to be 2 GHz, how much total time (in the number of nanoseconds) does it take to fill a cache block of 8 words in the event of a cache miss? (We assume a single-level cache.) How many CPU cycles is this total time equal to? (It is worth noting that the time you derived will be the worst- case cache miss cost, Cm.)