Question
Suppose that memory addresses are 16 bits and cache lines are 128 bytes in size. The system uses a single two-way set-associative cache of 8
Suppose that memory addresses are 16 bits and cache lines are 128 bytes in size. The system uses a single two-way set-associative cache of 8 lines. Starting with the initial cache state shown below, the system performs accesses to the following sequence of memory addresses:
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0xAC7D
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0x7E9D
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0x7699
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0x62BB
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0x7695
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0x39F1
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0x76DC
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0x98D7
Addresses of memory accesses
Line # | Tag |
0 | 0x12 |
1 | 0x45 |
2 | 0x3B |
3 | 0x58 |
4 | 0x58 |
5 | 0x0C |
6 | 0x1E |
7 | 0x3E |
Initial cache state (your answers to (a) and (b) should be shown in this format)
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How many bits are the offset, set number, and tag fields of memory addresses in this cache?
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Give the set number and tag (in hexadecimal) for each of the memory addresses that are accessed.
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If the cache is using the LRU replacement algorithm, say whether each access is a hit or miss. Show the final state of the cache in a table similar to the example below.
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Repeat (a) using FIFO replacement instead.
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