Suppose that the following instructions are found at the given locations in memory:

20 LDA 50

21 ADD 51

.

.

50 DAT 724

51 DAT 006

1. Show the contents of the IR, the PC, the MAR, the MDR and A at the conclusion of instruction at address 20.

2. Show the contents of each register as each step of the fetch-execute cycle is performed for instruction at address 21.