Suppose that you are given that the average miss rate for both L1 instruction cach and L1 data cache is 5%, and that the miss penalty is 50 cycles. You are given that the CPI with no cache misses is 1. You are also given the following data about instruction frequencies for ARMv8 architecture:

Load/Store: 35% Arithmetic: 45% Branches (all types) 20% A) Compute the CPI using the L1 cache miss rates and miss penalties. B) Suppose we added L2 cache. The miss rate of L2 is 1%. The access time of L2 is 10 cycles. Compute the CPI in this configuration. ---- Please neatly answer a and b. Include all steps and as much detail as possible, I will mark as helpful.