Suppose the following setup of a system which uses paging for address translation:

A virtual address $(VA)$ is $32-$bit long.

Page size: $2KB$

$(1)$ If linear paging is used, and page table entry $($PTE$)$ size is $32$ bytes, how many pages

do we need to store the linear page table $($LPT$)?$

$(2)$ If $2-$level paging is used where the LPT is divided into page$-$sized units, and both page

table entry $($PTE$)$ size and page directory entry $($PDE$)$ size are $32$ bytes, how many bits

are there for PDI, PTI and offset respectively?

$(3)$ Using the setting in $q-(2),$ suppose all the virtual pages in the address space of a process

$P$ are mapped with corresponding memory frames, how many pages are needed to store

the page directory and the page tables?

$(4)$ Using the setting in q$-(2),$ suppose only the first page and the last page in the address are

mapped with memory frames, how many pages are needed to store the page directory

and the page tables?

$(5)$ To further reduce the amount of memory to store the page directory and page tables

in the above setting $($i$.$e$.,$ q$-(4))$ by using $3-$level paging: specifically, the page directory

above is divided into page$-$sized units and introduce a top$-$level page directory to index

these units, how many pages are needed to store the page directories and page tables?