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Suppose the memory cells at addresses 00 through 07 in the machine described in Appendix C contain the following bit patterns: Address 00 2B 01

Suppose the memory cells at addresses 00 through 07 in the machine described in Appendix C contain the following bit patterns: Address 00 2B 01 07 02 3B 03 06 04 C0 05 00 06 00 07 23 List the addresses of the memory cells that are used to hold data.

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