Suppose the memory word address is 30-bit long and the cache size is 4K words for data. (We dont count the tag portion of the cache when the cache size is presented.)

A. If the cache is direct-mapped and has the block size is one word. How many bits should the block index have? How many bits should the word offset have? How many bits should the tag have? What is the total number of tag bits for this cache? If we define the ratio of total number of tag bits over total number of data bits as the tag-storage overhead, assuming each data word of size 64 bits, what is the tag-storage overhead?

B. Repeat (A) under the assumption that the cache is 4-way set-associative, and the block size is still one word.

C. Repeat (A) under the assumption that the cache is direct-mapped, but the block size is 4 words.

D. Repeat (A) under the assumption that the cache is 4-way set-associative and the block size is 4 words.