Suppose there is currently a $16$K words x $4$ bits SRAM.

$1.$Please draw a block diagram to design SRAM read circuitry that supports a $64-$bit output at once.

$2.$Following the previous question, please draw a block diagram to design SRAM circuitry that supports simultaneous read and write operations for $3$ SRAM units circuit, and each unit can reading and writing $4-$bit.