Suppose we have a pipelined processor with the following stages (8-stage pipeline - F1, F2, D1, D2, X, M1, M2, WB), with a branch predictor and a branch target buffer (BTB). Assume the following: Value loaded from Data Memory is ready at the of end of M2 Branches are resolved at the end of D2 stage Branch predictor achieves 90% accuracy. BTB misses 15% of the time for branches. BTB also stores jumps and the jump targets. For jum ps, BTB misses 10% of the time. Jumps are resolved in the Decode stage D1, in case of a BTB miss. BTB is accessed in the F1 stage Given the following workload description, calculate the CPI when this workload runs on the given processon. Workload: 25% of instructions are branches (beq, bne, etc). 10% are unconditional branches (jumps). 50% are ALU operations (add, addi, sub, etc) 15% of instructions are lw. * 40% of the instructions immediately following those loads (1w), have a dependency on the load. They use the loaded register, in the Execute stages. No other data dependencies exist in the entire workload. Assume that this set of instructions (ie, the 40% that have a dependency on the preceding lw) does not include any branch instructions. Suppose we have a pipelined processor with the following stages (8-stage pipeline - F1, F2, D1, D2, X, M1, M2, WB), with a branch predictor and a branch target buffer (BTB). Assume the following: Value loaded from Data Memory is ready at the of end of M2 Branches are resolved at the end of D2 stage Branch predictor achieves 90% accuracy. BTB misses 15% of the time for branches. BTB also stores jumps and the jump targets. For jum ps, BTB misses 10% of the time. Jumps are resolved in the Decode stage D1, in case of a BTB miss. BTB is accessed in the F1 stage Given the following workload description, calculate the CPI when this workload runs on the given processon. Workload: 25% of instructions are branches (beq, bne, etc). 10% are unconditional branches (jumps). 50% are ALU operations (add, addi, sub, etc) 15% of instructions are lw. * 40% of the instructions immediately following those loads (1w), have a dependency on the load. They use the loaded register, in the Execute stages. No other data dependencies exist in the entire workload. Assume that this set of instructions (ie, the 40% that have a dependency on the preceding lw) does not include any branch instructions