Suppose we want to pipeline the LC4 further. The problem will be that the memories have fixed delays. We can interleave mulitple memory banks to make the memories appear to be twice as fast as they actually are. Let's focus on the IMEM. As shown below, we split the 64K-word IMEM into two 32Kword memory banks. The ADDR[15:0] input comes from the LC4's PC, and the data_out[15:0] bus goes to the LC4's IR[15:0] bus. Design a FSM that controls memory bank access so that a new instruction can appear on the IR bus every clock cycle, if consecutive instruction addresses come from alternate memory banks. That is, if the first instruction has address 0000_0000_0000_0000 and the second instruction has address 0000_ 0000_0000_0001, the two instruction fetches will be separated by a delay of one clock cycle. Add muxes and registers as needed. Show all datapath and control wires and busses. Show a FSM state-transition diagram for the controller. Label each state with the control output signals for that state. Show the FSM's inputs and control signal outputs