Suppose you are given a $5-$stage pipeline architecture $($DLX processor$)$ and the pipeline stages are IF$=$instruction fetch, ID$=$instruction decode, EX$=$execution, MEM$=$memory access, and WB$=$ write back. Assume that the times required for the five functional units IF$,$ ID$,$ EX$,$ MEM, WB are as follows: $11$ ns$,8$ns$,9$ ns$,10$ ns$,$ and $7$ns$.$