Suppose you're working on a computer that has a CPU with the following characteristics:

• the CPU supports 20 bit addressing
• the CPU has a single level cache
• the cache has 512 rows
• each row in the cache holds 64 bytes
• the cache uses an 8-way set associative mapping function

Describe how the memory address is divided into fields for accessing the cache. Specifically, how many fields, and the width (number of bits) of each field, and the purpose of each field.