SW $t0, 4($sp)

Show how the following instruction is executed in aShow how the following instruction is executed in a multi cycle implementation of the MIPS CPU

Assume the instruction is in the EX stage.

Show what information and values will get stored in the ID/EX pipeline register above. Additionally indicate how many bits each value is.

ID/EX Information		Value and # of bits
WB
MEM
EX

ID/EX WB EX/MEM WB MEM/WB F/ID Add left 2 ALUSrc register 1 data 1 register 2 Write register Write ALU ALU Registers Read data 2 Instruction data Instruction 16 (15-0] MemRead Sign Instruction [20-16] 0 ALUOp [15-11] RegDst ID/EX WB EX/MEM WB MEM/WB F/ID Add left 2 ALUSrc register 1 data 1 register 2 Write register Write ALU ALU Registers Read data 2 Instruction data Instruction 16 (15-0] MemRead Sign Instruction [20-16] 0 ALUOp [15-11] RegDst