table 6.4

4. A CPU has the same register set and memory access as the Very Simple CPU, but a different instruction set. a) Complete the ISA by specifying the four new instructions, their instruction codes, and their overall functions. You can choose any functions you wish, but you must include at least one instruction that gets an operand from memory and at least one instruction that does not. (10/50) b) Show the state diagram and RTL code for the CPU. (20/50) c) Design the register section, ALU, and control unit for the CPU. Include the hardware to generate all control signals. Feel free to start with the hardware for the Very Simple CPU and modify it for the new CPU. (15/50) d) Trace the fetch, decode, and execute cycles for each instruction to verify the CPU implements the ISA correctly. Your solution should follow the format of Table 6.4.(5/50) Table 6.4 Execution trace Instruction ADD 4 AND 5 State Active Signals Operations Performed Next State FETCHI PCBUS, ARLOAD AR-0 FETCH2 FETCH READ, MEMBUS, DR-04H, PC-1 FETCH3 DRLOAD, PCINC FETCH3 DRBUS, ARLOAD, IR-00, AR--04H ADDI IRLOAD ADDI READ, MEMBUS, DR-27H ADD2 DRLOAD ADD2 DRBUS, ACLOAD ACO +27H = 27H FETCHI FETCHI PCBUS, ARLOAD AR-1 FETCH2 FETCH2 READ, MEMBUS, DR-45H, PC+2 FETCH3 DRLOAD, PCINC FETCH3 DRBUS, ARLOAD, IR-01, AR --05H ANDI IRLOAD ANDI READ, MEMBUS, DR39H AND2 DRLOAD AND2 DRBUS, ALUSEL, AC-27H A 39H - 31H FETCHI ACLOAD FETCHI PCBUS, ARLOAD AR-2 FETCH2 FETCH2 READ, MEMBUS, DR-COH, PC-3 FETCH3 DRLOAD, PCINC FETCH3 DRBUS, ARLOAD, IR-11, AR-OOH INCI IRLOAD INCI ACINC ACE21H + 1 - 22H FETCHI FETCHI PCBUS, ARLOAD AR-3 FETCH2 FETCH READ, MEMBUS, DR-80H, PC-4 FETCH3 DRLOAD, PCINC FETCH3 DRBUS, ARLOAD, IR-10, AR-OOH JMPI IRLOAD JMP1 DRBUS, PCLOAD PCO FETCHI INC JMPO