$\backslash$table$[[\frac{?}{\text{b}\text{a}\text{r}}($ Gate$\frac{\frac{?}{?}}{\text{I}}D),\backslash$table$[[0,1,2,3,4]],\backslash$table$[[6,7]],789],[$INV$,\backslash$table$[[1,2,1,2,3]],3,142],[$AND$,45,5,67],[$OR$,\backslash$table$[[,3,4,4,4]],5,67],[$NAND$,\backslash$table$[[3,4||,5,7]],\backslash$table$[[8,6]],9],[$NOR$,\backslash$table$[[3,4,5,5,6]],\backslash$table$[[86]],6],[$XOR$,,10,3109],[xNOR,\backslash$table$[[,6,7,9,10]],,]]$

Stages of the project:

The project is split into two stages of complexity, and you can choose how complex a system you wish to attempt to implement.

Stage $1$

The multiplier should be implemented using adders and the required gates. The first type of the adders to be used is the ripple carry adder which should be built structurally as follows:

Built $1-$bit full adder from the basic gates given above.

Use the full adder to build $4-$bit adder.

Use as many blocks as you need of the $4-$bit adder when you build the multiplier.

You should produce complete verification $($or large number of random cases$)$ to demonstrate the multiplier working as expected. You should determine the maximum latency of the multiplier. And therefore, what is the maximum frequency of clock that can be applied to the flip$-$flops. Also, you should introduce an error in your design and to do a verification that will discover the error.

Stage $2$

The second type of adders to be used is the carry look$-$ahead adder. You should implement a $4-$bit adder structurally using the basic gates given above. Use as many blocks as you need of the $4-$bit adder when you build the multiplier.

You should produce complete verification $($or large number of random cases$)$ to demonstrate the multiplier working as expected. You should determine the maximum latency of the multiplier. And therefore, what is the maximum frequency of clock that can be applied to the flip$-$flops. Also, you should introduce an error in your design and to do a verification that will discover the error.