Task \#1 1) Create a new Quartus Prime project with the following attributes: - Project Directory: lab3\ab3_task1 - Project Name: lab3_task1 - Top-Level Design: compare_2bit_scalar - Device: Cyclone IVE EP4CE115F29C7 (DE2), MAX 10 10M50DAF484C7G (DE10) 2) Navigate to and click on the Assignments > Settings... menu item in Quartus Prime. In the Settings dialog box, perform the following actions: 2 ECE 27001: Introduction to Digital System Design Spring 2023 - Click on the Compilation Process Settings category within the Category pane. In the Parallel Compilation section of the dialog box, click the Radio Button "Use all available processors". Then, click the OK button. 3) Use the Quartus Prime Text Editor to implement a Behaviorally model of a 2-bit magnitude comparator in a file named compare_2bit_scalar.sv. Specify the 2-bit magnitude comparator module according to the interface specification given in the table below. Within the implementation portion of the module, use a combination of continuous assignment statements and logic operators (i.e., AND, OR, XOR, NOT) to describe the 2-level ANDOR/OR-AND logic networks corresponding to the 2-bit magnitude comparator developed in prelab steps 5 and 6. 4) Perform an Analysis and Synthesis of the 2-bit magnitude comparator model. Ensure that the Quartus Prime Message Window shows zero errors and zero warnings. 5) Create a University Program Vector Waveform File (University Program _Vwf) named Waveform.vwf. Configure the .vwf file according to the following specification: - Edit the End Time to liss (if not already so). - Use the Overwrite Clock button to configure input port signals (a1,a0,b1,b0) (in order from top to bottom) such that all combinations of the four input port signals are generated in the waveform viewer during the lifetime of the simulation. - Edit the Grid Size such that it tracks the fastest changing group-signal. - Group input port signals a1 and a0 ( a lon top of a0 ) and name the group A. Then, change the Radix of signal group A to Unsigned Decimal. - Group input port signals b1 and b0 (blon top of b0 ) and name the group B. Then, change the Radix of signal group B to Unsigned Decimal. - Expand each grouped signal so the individual input port signals are visible. Now, perform a Functional Simulation of the 2-bit magnitude comparator model. For each input-group combination, verify the 2-bit magnitude comparator model correctly performs comparisons. Compare the functional simulation results to the truth table developed in pre-lab step 1. ECE 27001: Introduction to Digital System Design Spring 2023 6) View the technology independent schematic of the 2-bit magnitude comparator generated by Quartus Prime using the RTL Viewer. Compare the technology independent schematic to those developed in pre-lab steps 5 and 6 . 7) View the technology dependent schematic of the 2-bit magnitude comparator generated by Quartus Prime using the Technology Map Viewer (Post Mapping). Compare the technology dependent schematic to those developed in pre-lab steps 5 and 6. 8) Use the Quartus Prime Pin Planner to assign the I/O ports of the 2-bit magnitade comparator to the Cyclone IVE EP4CE115F29C7 (or Cyclone IVE EP4CE115F29C7) FPGA pins according to the assignments shown below. 9) Perform a Full Compilation of the 2-bit magnitude comparator model. Ensure that the Quartus Prime Message Window shows zero errors only. Ignore any wamings. 10) Perform a Timing Simulation of the 2-bit magnitude comparator model using the same .rwf created in step 4) of this task. Once again, verify the model of the 2-bit magnitude comparator correctly performs comparisons for each input combination. 11) Use the Quartus Prime Programmer to program the Cyelone IVE EP4CE115F29C7 (or MAX 10 10M50DAF484C7G) FPGA on the DE2-115 (or DE10) Development and Education Board. Test and demonstrate the functionality of the 2-bit magnitude comparator on the DE2115 (or DE10) Development and Education Board to a member of the teaching staff
