Task Three: Example Registers A SRAM memory word is modeled for you as a 8-bit D Latch register (page 3) in VHDL. The TA will give to youa bitstream file to load into the Basys3 and use the Enable signal to load test data and view results on the LEDs. a. (AA)s and b. (55)s 2. A Shift Register can be modeled in Logisim as a 8-bit Right Shift Register (page 4). The memory elements used in this case are D flip-flops which shift data one bit position per clock pulse. Build the 8-bit shift register in Logisim and perform the following tests: a. Set Dn high for 8 docks and fill-up the register. b. Set Dn low for 8 clocks and empty the register. C. Set Dn high for one clock to send a solitary high-bit down the register. Task Four: Android Galaxy Assembly We will now build a partial Galaxy phone mobile phone architecture using Xilinx which is capable of receiving and playing a music stream like Pandora using a Codec with a SRAM buffer. (This exercise will make use of the SRAM memory and shift registers examined in Task Three.) 1. We will send the Galaxy model as a Xilinx bitstream to a Basys2 board using the Digilent Adept software. Examine the contents of one of the sample 16-bit stereo wav audio files, using the HxD hex viewer. Go to: Programs-> Digilent->Adept and program a BASYS 2 board from the Config tab, via the FPGA. Go to the File I/O tab. In the Upload section, browse to the location of the sample audio files and select one. In the menu, check "Upload entire file" "Append" and "Upload entire file", and set "Register Address" to 0 2. 3. 4. 5. Click File>>Device. We will transfer the file to a 4096 16-bit word (n-12, m-16) SRAM in place of the SDRAM in the Galaxy block diagram. A progress bar indicates the file being transferred to. Format conversion (such as MP3 to wav) and format packaging (alternating 16 bits to the left and right channels) is done by the Audio Codec. Plug your headset (or earphones) into the stereo jack and listen to the streaming audio