TEN 3 CS ii. Register x9 contains the address Ox00000200. What is the value in register x5 after the following set of instructions? Did overflow occur? 1. lw x5, 0(x9) add x5, x0, x5 2. lw x5, 0(x9) add x5, X5, X5 4. Encode decoding RISC-V instructions (30 points) a Encode the following RISC-V instructions into hexadecimal: i add x5, x0, x6 11 lwu x5, 40(x6) lui sh x5, 2006) b. Decode the following RISC-V instructions from hexadecimal: OxO1DE02B3 Ox0102AE83 Ox01E2A023 v OX 12345287 5 c. What would be the impact on the RISC-V instruction set (R/\/S/U-formats) for the following 1. Doubling the number of registers i Can this change be accomplished and still maintain a 32-bit instruction word? iii. If so, what are the implications on each instruction type? 5. Arithmetic Logical instructions [20 points] a Assume the following values. =x5 g=x6, h=x7 Write RISC-V instruction sequences for the foitowing 0 =gah & a Assume the following values: F=x5, g=x6, h=x7. Write RISC-V instruction sequences for the following: i.f=0 f=g-h ii. f=g&H ivf=of vf= 329 v=18 vi f=1-1 Vi fagch ix = 2*g+h 6 Arrays (20 points) a. Assume the following C-Code segment int Array[4][2] = {{0, 1} (2,3), (4.5), (6,7}} Write the RISC-V equivalent initialization for row-order organization Write the RISC-V equivalent initialization for column order organization