TEST The verilog Code using a Testbench. I've copied my codes please follow the same stile and modify it so it works. You will need to the perform the operations in the table shown below in your test bench $($ALU$\_$tb$)$ and paste the waveforms showing successful operations.

Code:

$//$ ALU

module ALU $($input $[3$:$0]$ alu$\_$in$\_$a$,$ alu$\_$in$\_$b$,$ OPCODE, input Cin, output reg $[3$:$0]$ Sum, output reg Cout, output OF$)$;

reg $[3$:$0]$ Bin;

wire $[3$:$0]$ Bn$,$ S;

wire Co;

com$2$s C$1($alu$\_$in$\_$b$,$ Bn$)$;

ripple$\_$adder$\_4$bit FA$4($alu$\_$in$\_$a$,$ Bin, Cin, S$,$ Co$,$ OF$)$;

always @ $(*)$ begin

Bin $=4\text{'}$b$000$; Sum $=4\text{'}$b$0000$; Cout $=\text{'}$b$0$;

case $($OPCODE$)$

$//$ALU operations

$//0001$ A$+$B$+$Cin : add with Cin

$4\text{'}$b$0001$ : begin

Bin $=$ alu$\_$in$\_$b; Sum $=$ S; Cout $=$ Co;

end

$//0010$ A$+$B : add

$4\text{'}$b$0010$ : begin

Bin $=$ alu$\_$in$\_$b; Sum $=$ S; Cout $=$ Co;

end

$//0011$ A$-$B : sub a from b

$4\text{'}$b$0011$ : begin

Bin $=$ Bn; Sum $=$ S; Cout $=$ Co;

end

$//0100($alu$\_$in$\_$a&alu$\_$in$\_$b$)$ : bitwise NAND

$4\text{'}$b$0100$ : begin

Sum $=$ ~$($alu$\_$in$\_$a & alu$\_$in$\_$b$)$;

end

$//0101$ ~$($alu$\_$in$\_$a$|$alu$\_$in$\_$b$)$ : bitwise OR

$4\text{'}$b$0101$ : begin

Sum $=($alu$\_$in$\_$a $|$ alu$\_$in$\_$b$)$;

end

$//0110$ alu$\_$in$\_$a$^$alu$\_$in$\_$b : bitwise XOR

$4\text{'}$b$0110$ : begin

Sum $=$ alu$\_$in$\_$a$^$alu$\_$in$\_$b;

end

$//0111$ Bitwise NOT a

$4\text{'}$b$0111$ : begin

Sum $=$ ~alu$\_$in$\_$a;

end

$//0111$ Bitwise NOT a

$4\text{'}$b$0111$ : begin

Sum $=$ ~alu$\_$in$\_$a;

end

$//1000$ Logical Shift a right $1$ Bit

$4\text{'}$b$1000$ : begin

Sum $=$ alu$\_$in$\_$a $>>1$;

end

default : begin

Sum $=0$; Cout $=0$;

end

endcase

end

endmodule

$//4$ Bit Ripple Carry Adder

module ripple$\_$adder$\_4$bit$($input $[3$:$0]$ A$,$ B$,$ input Cin,output $[3$:$0]$ Sum, output Cout, OF$)$;

full$\_$adder FA$1($Sum$[0],$ Cout$1,$ A$[0],$ B$[0],$ Cin$)$;

full$\_$adder FA$2($Sum$[1],$ Cout$2,$ A$[1],$ B$[1],$ Cout$1)$;

full$\_$adder FA$3($Sum$[2],$ Cout$3,$ A$[2],$ B$[2],$ Cout$2)$;

full$\_$adder FA$4($Sum$[3],$ Cout, A$[3],$ B$[3],$ Cout$3)$;

xor X$1($OF$,$ Cout$3,$ Cout$)$;

endmodule

$//$ Twos Compliment

module com$2$s $($input $[3$:$0]$ B$,$ output $[3$:$0]$ Bn$)$;

wire $[3$:$0]$ Bn$1$;

wire OF;

assign Bn$1=$ ~B;

ripple$\_$adder$\_4$bit FA$4($Bn$1,4\text{'}$b$0000,1\text{'}$b$1,$ Bn$,$ Cout, OF$)$;

endmodule

$//$ Full Adder

module full$\_$adder$($output S$,$ Cout, input A$,$ B$,$ Cin$)$;

wire Sum$1,$ Cout$1,$ Cout$2$;

half$\_$adder HA$1($Sum$1,$ Cout$1,$ A$,$ B$)$;

half$\_$adder HA$2($S$,$ Cout$2,$ Sum$1,$ Cout$1)$;

or O$1($Cout$,$ Cout$1,$ Cout$2)$;

endmodule

$//$ Half Adder

module half$\_$adder$($output Sum, Cout, input A$,$B$)$;

assign Sum $=$ A$^$B;

assign Cout $=$ A&B;

endmodule

Te$//$ Test Bench Lab $2$

module tb$\_$alu;

$//$ Inputs

reg $[3$:$0]$ alu$\_$in$\_$a;

reg $[3$:$0]$ alu$\_$in$\_$b;

reg $[3$:$0]$ OPCODE;

reg Cin;

$//$ Outputs

wire $[3$:$0]$ Sum;

wire Cout;

wire OF;

$//$ ALU module

ALU uut $(.$alu$\_$in$\_$a$($alu$\_$in$\_$a$),.$alu$\_$in$\_$b$($alu$\_$in$\_$b$),.$OPCODE$($OPCODE$),.$Cin$($Cin$),.$Sum$($Sum$),$

$.$Cout$($Cout$),.$OF$($OF$))$;

$//$ Addition

initial begin

alu$\_$in$\_$a $=4\text{'}$b$0011$;

alu$\_$in$\_$b $=4\text{'}$b$0011$;

OPCODE $=4\text{'}$b$0010$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$; $//$ Output: $0110($#$6)$

$//$ Addition With Cin

alu$\_$in$\_$a $=4\text{'}$b$0110$;

alu$\_$in$\_$b $=4\text{'}$b$0101$;

OPCODE $=4\text{'}$b$0001$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$; $//$ Output: $1011($#$1)$

$//$ Subtraction

alu$\_$in$\_$a $=4\text{'}$b$0111$;

alu$\_$in$\_$b $=4\text{'}$b$0110$;

OPCODE $=4\text{'}$b$0011$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$; $//$ Output: $-1$

$//$ Bitwise NAND

alu$\_$in$\_$a $=4\text{'}$b$0111$;

alu$\_$in$\_$b $=4\text{'}$b$1010$;

OPCODE $=4\text{'}$b$0100$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$;

$//$ Bitwise OR

alu$\_$in$\_$a $=4\text{'}$b$0111$;

alu$\_$in$\_$b $=4\text{'}$b$0011$;

OPCODE $=4\text{'}$b$0101$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$;

$//$ Bitwise XOR

alu$\_$in$\_$a $=4\text{'}$b$0101$;

alu$\_$in$\_$b $=4\text{'}$b$1110$;

OPCODE $=4\text{'}$b$0110$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$;

$//$ Bitwise NOT

alu$\_$in$\_$a $=4\text{'}$b$1011$;

alu$\_$in$\_$b $=4\text{'}$b$0000$;

OPCODE $=4\text{'}$b$0111$;

Cin $=1\text{'}$b$0$;

#$5$;

$display$("$Sum $=\%$b$",$ Sum$)$;

$//$ Logical Right shift

alu$\_$in$\_$a $=4\text{'}$b$0101$;

alu$\_$in$\_$b $=4\text{'}$b$0000$;

OPCODE $=4\text{'}$b$1000$;