The aim of this task is to implement a Carry$-$Lookahead Adder $($CLA$)$ in SystemVerilog. The CLA is to add two n bit numbers together. It consists of $$ blocks for k columns each so that n $=-$ k$.$

Except for the testbench, it is not allowed to use addition operators, comparison operators or similar, use only operators from Boolean algebra $($Boolean reduction operators are allowed$).$

Note: You can also receive points for later parts of the task if you were unable to solve previous parts.

A CLA block for k columns is constructed as follows from the blocks RCA, GP and CARRY:

Implement the parameterized SystemVerilog module cla, which creates a CLA from several modules cla$\_$block for the individual CLA blocks. To do this, again use a generate block.

Note: You can assemble several CLA blocks in a similar way to how they are assembled in a Ripple$-$CarryAdder full adder. However, you must suitably divide the n bits into $$ blocks of length length k bits, so that each CLA block receives k bits each as A and B$.$

Note: If$,$ for example, you want to divide A into blocks of length k$,$ the lowest block is A$[$K$-1$:$0],$ the next block A$[2*$K$-1$:K$]$ and so on$.$ You could also divide specific values here by e$.$g$.$ the loop variable of the generate block.

Note: To test your code, you will have to design a testbench yourself in the next task. However, you can already compile your code now with the following command in order to test in with the empty testbench to check for correct syntax: Windows: $./$sim$.$bat cla, otherwise: $./$sim$.$sh cla'timescale $1$ns $/1$ns

module cla

#$($ parameter $K=4,$

$N=16)//$ you may assume here that $N$ is a multiple of $K,$ i$.$e$.,K,2K,3K,4K,$dots

$($ input logic $[N-1$:$0]A\frac{,}{\frac{?}{?}}$ Operand $A$

input logic $[N-1$:$0]B,//$ Operand B

input logic C$\_$IN$,//$ Carry$-$In

output logic $N-1$:$0$ SUM, $//$ Sum

output logic C$\_$OUT$)$; $//$ Carry$-$Out

localparam L $=$ N $/$ K; $//$ L instances of cla$\_$block needed

$10$