The AMD Bulldozer microarchitecture has a 16K, 4-way, 64-byte blocked LI data cache in each core. This processor uses 64-bit memory addresses. For this processor, please answer the following questions: When the L1 data cache receives a memory access request, how many bits will be used as "tag"? How many bits will be used as "index"? How many bits will be used as "offset"? In addition to the data array, the cache needs to contain tag arrays and dirty bits that are considered as overheads to the cache. Including these overheads, how many bits are required to build this cache