The circuit below shows the common source gain stage of an op-amp designed for the discrete amplifier project. The ALD1107 PMOS is the amplifying transistor and the ALD106 NMOS is its active load. The bias current is IDs-100 ??. The supply voltages are 5 V. The signal source resistance (the output resistance of the differential pair) is Rsig 150 k2. Take Cg,-500 ff, Cgd-5 fF, Cab-200 fF, and ? 0.033 Vi for both the NMOS and PMOS transistors. The total output capacitance of the preceding differential pair is modeled with Csig -1 pF, including the breadboard parasitics. The PMOS has kp-200 ??/V2, and the NMOS has k,-500 ??/V2. The load capacitance of CL-2 pF represents the input capacitance of the output stage (a) What is the unloaded mid-band gain, Avo, of the amplifier, in V/V? (b) Determine the pole frequencies associated with the input and output nodes, IN and OUT respectively (c) Comparing the ALD1106 and ALD1107, which one would give the larger gain and upper 3 dB frequency when used as the amplifying transistor? Why? olas 35