The classic five-stage pipeline MIPS architecture is used to execute the code fragments. Assume the followings:

Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle,

Branches are resolved in the second stage of the pipeline and the architecture does not utilize any branch prediction mechanism

Forwarding is fully supported.

Assuming there is no dependence other than one(s) given in the code, show the pipeline diagram.

Clock Cycle	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
add R4, R5, R6
lw R1, 0(R2)
beq R1, R4, target
I4