the code of experiment 2:

ALU module:

module ALU (A, B, Result, ALUSel, ZFlag); input [7:0] A, B; input [2:0] ALUSel; output reg [7:0] Result; output ZFlag; assign ZFlag = (Result==8'b0); always @ (*) begin case (ALUSel) 3'b000: Result = A + B; // addition 3'b001: Result = A - B; // subtraction 3'b010: Result = A - B; // subtraction 3'b011: Result = A - B; // subtraction 3'b100: Result = A | B; // bitwise OR 3'b101: Result = ~(A | B); // bitwise NOR 3'b110: Result = A & B; // bitwise AND 3'b111: Result = A ^ B; // bitwise XOR endcase end endmodule

Binary counter:

module binary_ctr #(parameter x = 3, n = 8) (clk, reset, en, count); input clk, reset, en; output reg [x-1:0] count; always @(posedge clk, posedge reset) begin if (reset == 1 ) count

Reg file:

module regFile (clk, rst, A_data, B_data, W_data, A_addr, B_addr, W_addr, wr); input clk, rst; output[7:0] A_data, B_data; input[7:0] W_data; input[3:0] A_addr, B_addr, W_addr; input wr; // declaring array of 16 8-bit registers - Register File reg[7:0] RegFile[0:15]; // Reading registers assign A_data = RegFile[A_addr]; assign B_data = RegFile[B_addr]; // Writing to a register always @ (posedge clk) begin if(!rst) if(wr) RegFile[W_addr]

ROM:

module rom(input [5:0] addr, output [25:0] data_out); reg [25:0] mem [0:63]; assign data_out = mem[addr]; initial begin mem[0]= 26'b00000000000011000001111101; mem[1]= 26'b00000000000111000000011110; mem[2]= 26'b00000000001011000011001001; mem[3]= 26'b00000001101010011000000000; mem[4]= 26'b00000010101110011100000000; mem[5]= 26'b10101011110010000000000000; end endmodule

Top module:

module topmodule(clk, rst, W_data); input clk, rst; output [7:0] W_data; wire [7:0] result; wire [5:0] bout; wire[25:0] mem; wire zflag; wire [7:0] a; wire [7:0] b; binary_ctr #(6,64) bctr (.clk(clk), .reset(rst), .en(1'b1), .count(bout)); rom rom (.addr(bout), .data_out(mem));

regFile regf (.clk(clk), .rst(rst), .A_data(a), .B_data(b), .W_data(W_data), .A_addr(mem[25:22]), .B_addr(mem[21:18]), .W_addr(mem[17:14]), .wr(mem[13])); ALU alu (.A(a), .B(b), .Result(result), .ALUSel(mem[10:8]), .ZFlag(zflag));

assign W_data = mem[12] ? mem[7:0]:result; /*always @ (*) begin if(mem[12] == 0) result = W_data; else result = mem[7:0]; end endmodule*/ endmodule

2. [3 Pts] Update Exp2 to implement the full architecture shown in figure 2, after adding data1. Note that datal should now be added to the ROM word. 3. [2 Pts] Write a microprogram to do the following operation: w=(x2&y)+(xz)+187 where x= 125,y=30,z=201. You should divide this operation to micro-operations and fill in a table for the instruction word for each micro-operation, same as you did in Exp1. 4. [4 Pts] Write a testbench to simulate the datapath of Q2, using the microprogram of Q3. Attach a screenshot of the simulation waveform output on Vivado