The critical path latencies for the 7 major blocks in a simple processor are given below. Control 100ps a. I-Mem Add Mux ALU Regs D-Mem 400ps 100ps 30ps 140ps 200ps 350ps b. 500ps 150ps 100ps 180ps 320ps 1000ps 65ps For each part, answer the following questions: 1. What is the critical path for a MIPS ADD instruction? Explain your break-up. 2. If the number of registers is doubled, this increases Regs by 100ps and Control by 20ps. This results in 10% fewer instructions due to fewer load/stores. What is the new critical path for a MIPS ADD instruction?