To avoid lengthening the critical path of the datapath shown in Figure 4.24, how much time can the control unit take to generate the MemWrite signal?

In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies:

Transcribed Image Text:

PC Instruction [25-0] Add Read address Instruction [31-0] Instruction memory 26 Shift left 2/ Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Instruction [15-0] Jump address [31-0] PC +4 [31-28] Control Ox 28 RegDst Jump Branch MemRead MemtoReg ALUOD MemWrite ALUSrc RegWrite Read register 1 Read register 2 16 Read data 1 Write Read register data 2 Write data Registers Sign- extend Instruction [5-0] 32 Shift left 2, XCO Add ALU result Zero ALU ALU result ALU control/ Address 0 o MX- 1 Read data Write Data data memory MUX MUX