The delays of multiplexers, control unit, shifters, and sign extension unit are assumed to be zero. (a) Identify which figure above corresponds to the single cycle architecture and which to the multi-cycle architecture. (b) Calculate the maximum clock speed (in Hertz) allowed in the single cycle and multi-cycle architectures respectively? (c) For a program with 40% R type, 40% I type and 20% J type instructions, which implementation is faster?

Consider the single cycle and multi-cycle implementations of the MIPS processor shown in the figures below The time taken by each component in each of the two architectures is as follows: Instruction Memory Access 200 p - Register File read from stable read-register number 100 ps ALU delay 100 ps Data Memory Access (read) Write into registersmemory from rising edge of clock 50 pa 300 ps - (wbere p: stands for pico-econds (10 econd)