The design of the GCD calculator should have a controller and a datapath. The controller is an FSM which issues

commands to the datapath based on the current state and the external inputs. This can be a behavioral description.

The datapath contains a netlist of functional units like multiplexors, registers, subtractors and a comparator, and

hence this design is structural. The Datapath does the actual GCD computation. It has the following components:

Mux: takes $24-$bit inputs and one select line. Based on the select line, it outputs either the $1$st $4-$bit number

or the $2$nd $4-$bit number.

Register: Takes a $4-$bit input, a load signal, reset, and a clock signal. If the load signal is high and the clock

is pulsed, it outputs the $4-$bit number.

Comparator: Takes $24-$bit numbers, and assets one of $3$ signals depending on whether the $1$ st number is

less than, greater than or equal to the $2$ nd number.

Subtractor: Takes $24-$bit numbers, subtracts the smaller number from the larger.

Output Register: Holds the GCD value. When $x=y$ the GCD has been found and can be outputted.

Because it is a register entity it should also take a clock and reset signal.

$x=10$

$y=2$

Is $x=y?$ No$,x>y$ therefore $x=x-y$

in our case, $x=10-2=8.$

Is $x=y?$ No$,x>y$ therefore $x=x-y$

In our case, $x=8-2=6.$

Is $x=y?$ No$,x>y$ therefore $x=x-y$

In our case, $x=6-2=4.$

Is $x=y?$ No$,x>y$ therefore $x=x-y$

In our case, $x=4-2=2.$

Is $x=y?$ Yes, therefore the GCD of $10$ and $2$ is $2.$

Create an FSM to reflect the GCD calculation process.

Convert the FSM to an FSM $+$D

Write the Verilog code to reflect the controller and data path.

Write a test bench and verify the correctness of your design