The figure below shows the state transition diagram of a finite state machine $($FSM$)$ that is designed for

the purpose of detection of two unique sequences of codes and the entity diagram for its intended operation.

A

The outputs of the FSM are defined in the following table:

Input A is a synchronous single$-$bit data input. State transitions may occur at every rising clock edge on

the synchronizing clock input clk$.$ A bit stream should be applied on input A and based on the state of B$,$

the FSM can detect either the sequential code $"1001"$ when $B=\text{'}0\text{'}$ or the code $"1011"$ when $B=\text{'}1\text{'}.$The figure below shows the state transition diagram of a finite state machine $($FSM$)$ that is designed for

the purpose of detection of two unique sequences of codes and the entity diagram for its intended operation.

A

The outputs of the FSM are defined in the following table:

Input A is a synchronous single$-$bit data input. State transitions may occur at every rising clock edge on

the synchronizing clock input clk$.$ A bit stream should be applied on input A and based on the state of B$,$

the FSM can detect either the sequential code $"1001"$ when $B=\text{'}0\text{'}$ or the code $"1011"$ when $B=\text{'}1\text{'}.$