The following code is to be run on the pipelined MIPS CPU which stalls on data hazards and does not forward. 1. gi 'this branch is not taken beq $t1, $0, tar addi a0, a0, 4 add $t1, $t1, $t3 lw t1, 0 (St1) Show the pipeline timing on the diagrams for the following conditions. Use the two- letter abbreviations for each stage: IF, RF, EX, M, WB Assume stalling for both control (branch) hazards and data hazards. For control hazards, IF of the dependent (later) instruction aligns with WB of the earlier instruction. For data hazards, RF of the dependent instruction must follow WB of the earlier instruction. a. Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 21 22 lw $t1, 0($a0) beq $t1, $0, targ1 addi $a0, $a0, 4 add $t1, $t1, t3 lw St1, 0(St1) add $vO, vO, $t1 b. Improve the pipeline by adding branch prediction. Assume the branch is predicted correctly, and diagram below. Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 21 22 lw $t1, 0($a0) beq $t1, $0, targ1 addi $a0, $a0, 4 add $t1, t1, $t3 lw $t1, 0(St1) add Svo, vo, $t1 c. Further improve the pipeline by adding register forwarding. Diagram below Cycle 0 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 21 22 beq $t1, $0, targ1 addi $a0, $a0, 4 add $t1, t1, t3 lw $t1, 0(Sti) add Svo, Svo, t1