Q1. Consider I have a 7-stage pipeline, with instruction decoding happening at the third stage, execution in the fourth stage, memory in the fifth stage, and write back in the seventh stage. Consider the execution of the following instructions using this architecture. (Each stage takes exactly one clock cycle). Id x7, 64(x8) add x8, x7, x12 sd x7, 64(x8) a) How many stall cycles need to be inserted to correctly execute these instructions in the hardware without a forwarding logic?..... ---(1 credit) Ans: b) How many stall cycles need to be inserted to correctly execute these instructions in the hardware with a forwarding logic? ------(1 credit) Ans c) What is the total number of clock cycles needed to execute these three instructions in the hardware with a forwarding logic (assuming the pipeline was initialized and empty prior to executing these instructions)?-- --(2 credits) Ans: