Question
The following Figure illustrates a system that has L1 and L2 caches between the CPU and the main memory. CPU - L1 cache - L2
The following Figure illustrates a system that has L1 and L2 caches between the CPU and the main memory.
CPU - L1 cache - L2 cache - Main memory
The L1 cache, L2 cache, and main memory, have access times of 1, 10, and 100 cycles respectively. Assume that the L1 and L2 caches have miss rates of 5% and 20%, respectively. What is the average memory access time (Tav)?
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Introduction To Database And Knowledge Base Systems
Authors: S Krishna
1st Edition
9810206208, 978-9810206208
