The following has to be coded in SystemC: Design and verify a communications interface. Often data sent over a data link are organized as packets of data, each packet containing some identification bits, data, and some check bits used to determine if a transmission error has occurred. Your hardware must meet the following specification:

Inputs: Clock; Reset; //reset is active low Clear; //clears output registers active high InData[11:0]; // Input data, organized as follows: // InData[11:8] contains the `header // InData[7:4] contains the `data payload // InData[3:1] are not used // InData[0] is a parity bit. It is `1 if InData[7:4] is meant to be even parity. // A new `InData arrives every clock

Outputs: All outputs are registered and are cleared when `reset is low or `clear is high. Payload[3:0]; // is changed to contain the `data payload when `InData is of type 1. Count[7:0]; // total count of type 1 datas Error[7:0]; // number of type 1 datas of wrong parity

Clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Clear 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

InData 1F1 0E0 171 0E0 (i.e., 1F1 : `type 1, payload=F, parity should be even 0E0 : `not type 1, payload=E, odd parity 170 ; `type 1, payload=7, payload should have been even parity Payload 0 F F 7 7

The piece of hardware checks InData on each clock cycle. If InData[11:8] = 1, then it transfers the middle four bits of InData to payload and increments count. At the same time, it checks the parity of the middle four bits and sees if it is as expected. If it is not, then there is a transmission error, and error is incremented