The following is the schematic of a combinational CMOS gate: (a) What is the logic expression that describes the functionality of this gate? (b) On the schematic above, size the transistor widths to give the same effective rise and fall resistances as a unit inverter. (c) Ignoring transistor sizes, draw a stick-diagram layout of this cell. (d) Estimate the area of the cell assuming unit size transistors (e) Estimate the area of the cell using transistor sizes you calculated in part (b), allowing an extra (w-1).42 of height for a width-w transistor) (1) The schematic is redrawn below. Based on the transistor sizes you determined in part (b). assign effective resistances to each transistor and effective capacitances to each node in the circuit. (g) What is the worst case rising propagation delay if the output is driving three unit sized 2- (h) What is the input transition that will lead to this worst case delay? (2 pts extra credit) input NAND gates? Your answer should be of the form: (da, Bo. Co. Do. Eo) (Al, B, C1. D. E) where Ao is the value of input A before the transition and A is the value of imput A after the transition